1. Field of the Invention
The present invention relates to voltage level detection, and in particular, to a voltage level detecting circuit that reduces power consumption in a stand-by state and stably operates despite circuit noise.
2. Background of the Related Art
A related art voltage level detecting circuit for detecting a voltage (Vcc) is shown in FIG. 1. In the related art voltage level detecting circuit, a plurality of NMOS transistors (NM1-NM4) having their drains connected to their gates are series connected and the voltage (Vcc) is applied to the gate of the first NMOS transistor (NM1). The series connected NMOS transistors (NM1-NM4) are also connected by the drain of NMOS transistor NM4 to a drain of an additional NMOS transistor (NM5) through a connecting point (N1). The source of the additional NMOS transistor (NM5) is grounded (Vss). The voltage from the connecting point (N1) passes through series inverters (IN1, IN2) and is output as a voltage level detecting signal (OUT).
The operation of the related art voltage level detecting circuit shown in FIG. 1 will now be described.
When power is input to an apparatus, the level of the voltage (Vcc), which is the voltage to be detected, is increased. As the voltage (Vcc) sequentially passes through the series connected NMOS transistors (NM1-NM4), the voltage level drops by each transistor threshold voltage (Vt), respectively, and the resulting voltage appears at the node (N1).
The voltage (Vcc) is also applied to the gate of the additional NMOS transistor (NM5).
When the voltage level of the node (N1) is lower than a threshold voltage of the inverter (IN1), the voltage input to the inverter (IN1) is determined to be low. The low input voltage passes sequentially through the invertors (IN1, IN2) to output a low level voltage level detecting signal (OUT).
Then, as the level of the voltage (Vcc) is gradually increased (and dropped through the series connected NMOS transistors (NM1-NM4)), the voltage level at the node (N1) also increases. When the voltage level at the node (N1) becomes higher than the threshold voltage of the inverter (IN1), the inverter (IN1) determines that the input voltage is high. In this case, the high voltage from the node (N1) passes sequentially through the inverters (IN1, IN2) to output a high level voltage level detecting signal (OUT).
In the related art operation for detecting the voltage level, as the level of the voltage to be detected increases the level of the voltage level detecting signal is maintained low for a predetermined time. When the level of the voltage (Vcc) exceeds a preset level, the voltage level detecting signal is momentarily changed into a high level signal as shown in FIG. 2.
However, since the related art voltage level detecting circuit has a current path between the voltage (Vcc) and ground, much power continues to be consumed. Further, the level of the voltage level detecting signal changes to the low level when the level of the detected voltage drops below the preset voltage. Accordingly, near the preset voltage, the value of the voltage level detecting signal can fluctuate between high and low because of noise. Thus, stable operation of the related art voltage level detecting circuit cannot be achieved.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.